1. Field of the Invention
The present invention generally relates to preventing undesirable behavior on a computer bus. More particularly, the invention relates to the use of proxy logic to detect the onset of a condition which, if undetected, would lead to undesirable bus behavior and to prevent the undesirable behavior from occurring.
2. Background Information
As is commonly known, computers include central processing units (“CPUs”), memory, bridge logic devices, and other types of devices all generally coupled together via one or more busses. A bus comprises collection of individual data, address and control signals which coordinate the efficient transmission of commands and responses through the computer. Various electronic devices connect to a bus over which they send and receive messages. To avoid confusion, each bus device typically is assigned a unique address to permit messages, packets, etc. to be sent to specific device(s). Bridge logic can be used to connect together two or more busses to permit the system to be scaled as desired.
On many busses, operation typically entails one entity on the bus (called the “master”) initiating a transaction to another entity on the bus by transmitting a request containing the address of the target device. Although all of the devices may receive the request, only the intended recipient successfully decodes the address as its own and “claims” the cycle. Once the target claims the cycle, the cycle is permitted to run. The cycle might be a read request in which the master requests data from the target, a write request by which the master provides new data to the target, a configuration cycle, etc.
Several situations can lead to undesirable bus behavior. These situations have been observed on a Peripheral Component Interconnect (“PCI”) bus, although the problems may not be unique to PCI busses. Before these situations are discussed, a brief overview of the operation of the PCI bus is provided. When a master desires to initiate a cycle on a PCI bus, the master asserts a PCI bus signal called FRAME# (where the symbol # that indicates the signal is considered asserted in a low logic state). The master also places the address of the intended target and the command type on the PCI bus's address/data and command/byte enable lines. Of all of the devices on the bus, only the target with the matching address claims the cycle as its own. The target claims the cycle by asserting another PCI signal called DEVSEL# which indicates to the master that the target device has correctly decoded the address.
The PCI specification permits four types of decode possibilities. A “fast” decode is when the target device decodes the request and asserts DEVSEL# to claim the cycle one clock cycle after the address and command is presented. In a “medium” decode condition, the target device asserts DEVSEL# two clocks after the address and command is presented. A “slow” decode occurs when the target asserts DEVSEL# three clocks after the address and command is presented. Finally, the PCI specification suggests having one device on the bus being designated to act as a “subtractive” decode agent which will assert DEVSEL# on the fourth clock cycle after the address and command are presented if no other device has already claimed the cycle via a fast, medium or slow decode. The subtractive decode agent may not be the intended target, but claims the cycle nonetheless to ensure proper operation of the bus. Once a target device claims the cycle, the cycle completes in various ways consistent with the PCI specification.
As noted above, several situations can lead to undesirable bus behavior. For instance, some bus devices occasionally may be unable to respond properly. For example, a PCI add-in card may contain its own logic that, at times, may be in a state that prevents the card from responding correctly to a PCI cycle. That is, the card may respond to an attempted PCI cycle, but not do so in full compliance with the PCI specification. In one scenario, it has been observed that a PCI target device on a card correctly decoded the address on the bus as its own and responded by asserting DEVSEL. However, the PCI target device subsequently failed to terminate the cycle properly thereby causing the cycle to hang up, effectively locking the bus. This occurred when, for example, the host computer system placed the PCI target device into an initialization or test mode of which the add-in card was unaware.
Another situation may occur when the intended target device has been transitioned to a non-responsive mode of operation. This may occur when the host CPU has disabled the controller from responding at all to a PCI bus cycle. Some systems have a second processor. For example, in some server applications, the system includes a management processor which, among other things, permits a user at a remotely located console to interact with the server to configure the server and check its status. Some systems have been designed so that the management processor functions generally autonomously from the host server's CPU, thereby permitting a remote console to access logic on the server even if the server's main CPU is non-operational. For example, if a PCI bus device is a video graphics controller which contains data to be displayed, the management processor can access the card's display data in the card's memory even when the server's CPU is in a non-functional state. For various reasons (simplicity, cost, space limitations, etc.), the management processor may be connected to the same PCI bus as the server's main CPU. As such, the management processor shares the infrastructure resources of the server with the main CPU.
The autonomous nature of the management processor means that the management processor may be unaware that the main CPU has disabled a PCI bus device (e.g., the graphics card). Thus, the management processor may issue a cycle to a PCI device bus device that is incapable of responding without being aware that the device cannot respond. If the intended recipient of the PCI bus cycle is unable to respond at all within the fast, medium or slow decode time periods, the bus's subtractive decode agent will claim the cycle. The subtractive decode agent may comprise a bridge logic device which bridges the primary PCI bus to other bus's and logic. The subtractive decode agent further may attempt to pass the cycle it has now claimed on to its subordinate busses/logic. The subtractive decode agent also may request the management processor to retry the cycle at a later time, thereby giving the subtractive decode agent sufficient time to process the cycle. While the subtractive decode agent is processing the cycle, the server's CPU may enable the previously disabled intended target. Then, the next time the management processor retries the PCI bus cycle, the true intended target will claim the cycle. At that point, both the intended target and the subtractive decode agent have claimed the same cycle. This condition is known as bus “contention” and can lead to unpredictable bus behavior, and therefore unpredictable system behavior.
Accordingly, a solution to these problems of improper bus behavior is needed.